1. Field of the Invention
The present invention relates generally to the design of analog to digital converters (ADC), and more specifically to a technique for reducing power consumption in the early stages of a pipelined sub-ADC in a time-interleaved ADC.
2. Related Art
An analog to digital converter (ADC) is generally used to sample an analog signal at various time instances, and generate a digital code representing the strength (of voltage or current) of the sampled analog signal at the corresponding time instance.
Time interleaved ADC is a type of ADC in which multiple individual ADCs (conveniently hereafter referred to as sub-ADCs) are operated in parallel, with each sub-ADC sampling a corresponding successive sample of the analog input signal in a time-interleaved fashion. The samples generated by the sub-ADCs are then multiplexed into a single stream to represent the output codes generated by the interleaved ADC. Due to such an operation, each sub-ADC may be designed for lower sampling rates, while the time interleaved ADC provides high overall sampling rates.
Pipelined ADCs are often used to implement sub-ADCs in a time-interleaved ADC. A pipelined ADC is a type of ADC which contains a sequence of (pipelined) stages, with each stage resolving a number of bits forming a sub-code. The sub-codes generated by various stages are used to generate a digital code corresponding to the analog input sampled by the corresponding sub-ADC.
Each stage (except the last stage) of a pipelined ADC generates a residue signal representing that portion of the input signal that needs to be resolved by subsequent stages. The residue signal represents a difference of the voltage of the input signal to the stage and the voltage level corresponding to the sub-code provided by the stage. The residue signal (in an amplified form, typically) of one stage is provided as an input signal to the next stage in the sequence. In general the first stage represents an early stage (since the sample is processed first by the first stage) in the sequence.
There is a general need to reduce power consumption in ADCs, and in particular the early stages of pipelined sub-ADC. Such reduction is of concern in early stages since early stages are generally implemented using components consuming a large amount of power, for enhanced accuracy and/or performance, as is well known in the relevant arts.
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